Publications

2009

  1. Poster presentation. European Nano-Electronics Forum 2009 Noordwijk. The Netherlands. (Sep 2009)
  2. Gligor, M.; Fournel, N.; Pétrot, F., Using Binary Translation in Event Driven Simulation for Fast and Flexible MPSoC Simulation. International Conference on Hardware-Software Codesign and System Synthesis, (Oct 2009).(Partner: TIMA)
  3. Flich, J.; Duato, J.; Camacho Villanueva, J.; Eberle, H.; Gura, N.; Olesinsk, W., A Performance Evaluation of 2D-Mesh, Ring, and Crossbar Interconnects for Chip Multi-Processors. NoCArc 2009.(Partner: UP Valencia) (Dec 2009)

2010

  1. Arkesteijn, V.; Schinkel, D., ADC’s en DAC’s veel meer dan componenten in de marge, Bits & Chips, no. 2, (Feb 2010). (Partner: Axiom IC)
  2. Vivet, P.; Beigne, E.; Lebreton, H.; Zergainoh, N., On line Power Optimization of Data Flow Multi-Core Architecture based on Vdd-Hopping for Local DVFS, Proc. of International Workshop and Power and Timing Modelling Optimization and Simulation, PATMOS’2010 (Sept 2010).(Partner: CEA Leti)
  3. Goossens, K.; She, D.; Milutinovic, A.; Molnos, A., Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications, Proc. of DSD, (Sep 2010). (Partner: TUDelft)
  4. Bhatti, M.K.; Belleudy, C.; Auguin, M., An Inter-Task Real Time DVFS Scheme for Multiprocessor Embedded Systems, Proc. of International Conference on Design and Architectures for Signal and Image Processing, DASIP’10, Edinburgh, UK. (Oct 2010).(Partner: University of Nice)
  5. Kriegel, J.; Broekaert, F.; Pegatoquet, A.; Auguin, M., Power optimization technique applied to real-time video application, 13th Sophia Antipolis Microelectronics Forum (SAME), University Booth, Valbonne, France. (Oct 2010). (Partner: University of Nice)
  6. Nelson, A.; Moreira, O.; Stuijk, S.; Molnos, A.; Goossens, K.; Nguyen, B.T., Ideas on Power Minimisation for Real-time Dataflow Applications Through Voltage & Frequency Scaling. Proc. Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress). (Nov 2010).(Partner: TUDelft)
  7. Chandrasekar, K.; Akesson, B.; Goossens, K., Modeling and Optimizing Power for a Real-Time SDRAM Controller, Proc. Annual Workshop on PROGram for Research on Embedded Systems & Software (Progress). (Nov 2010).(Partner: TUDelft)
  8. Bhatti, M.K.; Belleudy, C.; Auguin, M., Power Management in Real Time Embedded Systems through Online and Adaptive Interplay of DPM and DVFS Policies, Proc. of International Conference on Embedded and Ubiquitous Computing, EUC’10, Hong Kong, SAR, China. (Dec 2010).(Partner: University of Nice)
  9. Simon Louwsma, Successive Approximation ADCs, Bits & Chips Hardware Conference, Eindhoven, The Netherlands. (June 2010). (Partner: Axiom-IC)

2011

  1. Bhatti, M.K.; Belleudy, C.; Auguin, M., Hybrid Power Management in Real Time Embedded Systems: An Interplay of DVFS and DPM Techniques, Springer Journal on Real Time Systems, Special Issue on Temperature/Energy Aware Real-Time Systems. (2011) (Partner: University of Nice)
  2. Pétrot, F.; Fournel, N.; Gerin, P.; Gligor, M.; Hamayun, M.; Shen, H., On MPSoC Software Execution at Transaction-Level, IEEE Design & Test of Computers 2011. (DATE 2011). (March 2011).(Partner: TIMA)
  3. Michel, L.; Fournel, N.; Pétrot, F., Speeding-up SIMD instructions Dynamic Binary Translation in Embedded Processor Simulation, Design, Automation & Test in Europe (DATE 2011). (March 2011).(Partner: TIMA)
  4. Zaykov, P.G.; Kuzmanov, G., Architectural Support for Multithreading on Reconfigurable Hardware, International Symposium on Applied Reconfigurable Computing (ARC 2011), Belfast, United Kingdom. (March 2011). (Partner: TUDelft)
  5. Cano, J.; Flich, J.; Duato, J.; Coppola, M.; Locatelli, R., Efficient Routing Implementation in Complex Systems-on-Chip. NoCs. (May 2011).(Partner: UP Valencia)
  6. Dubois, F.; Cano, J.; Coppola, M.; Flich J.; Pétrot, F., Spidergon STNoC Design Flow. NoCs 2011. (May 2011).(Partners: TIMA and UP Valencia)
  7. Isaza, S.; Sanchez, F.; Cabarcas, F.; Ramirez, A.; Gaydadjiev, G., Parametrizing Multicore Architectures for Multiple Sequence Alignment, ACM Computing Frontiers (CF 2011), Ischia, Italy. (May 2011). (Partner: TUDelft)
  8. Beigne, E.; Vivet, P., An Innovative Local Adaptive Voltage Scaling Architecture for On-chip Variability Compensation, IEEE Conference on New Circuits and Systems Conference (NEWCAS), 2011. (June 2011).(Partner: CEA Leti)
  9. Isaza, S.; Houtgast, E.; Sanchez, F.; Ramirez, A.; Gaydadjiev, G., Scaling HMMER Performance on Multicore Architectures, International Conference on Complex, Intelligent and Software Intensive Systems (CISIS), (July 2011). (Partner: TUDelft)
  10. Chandrasekar, K.; Akesson, B.; Goossens, K., Improved Power Modeling of DDR SDRAMs, DSD 2011. (Sep 2011).(Partner: TUDelft)

PATENTS

2009

  1. ST-Ericsson, Mobile wireless receiver front end with multiple inputs, submitted 2009.
  2. ST-Ericsson, Dynamic adaptive cohabitation scheme for NFC and FM, submitted 2009.

2010

  1. ST-Ericsson, Power-efficient branch prediction, submitted 2010.
  2. ST-Ericsson, Improved scalar distribution in an SIMD system, submitted 2010.
  3. UPV, Routing Method for on-chip communication, submitted 2010.

2011

  1. ST-Ericsson, Method for the static assignment of discrete frequency/power operating points to tasks of a real-time application running on a DVFS-enabled multiprocessor, submitted 2011.